Not applicable.
The present invention relates generally to testing an integrated circuit die on a wafer without physically probing its bond pads and, more particularly, to testing the pad buffers, electrostatic discharge protection circuitry, and pad bus holders of the die without physically probing the bond pads.
Scan testing of circuits is well known. Scan testing configures the circuit into scan cells and combinational logic. Once so configured, the scan cells are controlled to capture test response data from the combinational logic, then shifted to unload the captured test response data from the combinational logic and to load the next test stimulus data to apply to the combinational logic.
FIG. 1 shows an electrical circuit having three memories (M) A, B, C and combinational logic (CL). FIG. 2 shows an example of the memories of FIG. 1 implemented as D flip flops (FF), each memory having a data input, data output, and clock and reset control signals. FIG. 3 shows one example of how the circuit of FIG. 1 can be made scan testable by converting the memories into scan cells and connecting the outputs (D, E, F) of the combinational logic to the scan cell capture inputs. FIG. 4A shows an example of how a D flip flop based memory is converted into a scan cell. The scan cells have a 3:1 multiplexer input to the flip flop. The multiplexer receives selection control (S) to: (1) input the output of the combinational logic to the flip flop (Input1, the capture input), (2) input the external input to the flip flop (Input2, the functional input), or (3) input the serial input to the flip flop (SI, the shift input). The flip flop receives a clock (C) and a reset (R) control input. The scan cells are connected together via their serial input (SI) and serial output (SO) to form a 3-bit scan path through the circuit of FIG. 3. The three scan cells operate as the state memories during functional operation. During test operation, the scan cells operate as scan cells to allow inputting test stimulus to the combinational logic and capturing the response output from the combinational logic. While edge sensitive D flip flop memories are used in this disclosure, level sensitive memories could be used as well. Converting level sensitive memories into scan memories is well known.
In the FIG. 3 example, the scan cells perform both the input of stimulus to the combinational logic and the capture of response from the combinational logic. In other examples of how the circuit may be made scan testable, scan cells could be added to the circuit and scan path, and coupled to the outputs of the combinational logic, as shown in the dotted boxes in FIG. 3. This would allow the input stimulus to be supplied by the converted scan cells (A, B, C) and the output response captured by the added scan cells. Adding scan cells for the purpose of capturing response data adds circuitry. Also if scan cells are added to capture the combinational logic response, the converted scan cells A, B, C do not need Input1 and the feedback connections from the combinational logic outputs.
Also in FIG. 3 a bypass memory (BM) is shown to allow a single bit bypass scan path through the circuit from SI to SO. The use of scan bypass memories is well known. An example of the bypass memory is shown in FIG. 4B. In addition to providing conventional bypassing of the circuit, the bypass memory of the present invention is required to maintain its present state during capture operations, and to always load data from SI regardless of whether it is selected between SI and SO or not. The multiplexer of the bypass memory and the selection (S) control it receives allow these two requirements to be met.
FIG. 5 shows three of the circuits of FIG. 3 connected in series to a tester. The tester outputs data to the serial input of the first circuit (C1) and receives data from the serial output of the last circuit (C3). The tester outputs control to all three circuits to regulate their scan cell""s capture and shift operations during each scan test cycle.
FIG. 6 shows the concept of conventional scan testing. In FIG. 6, N circuits are connected on a scan path. A tester controls all circuits C1-N to reset. Following reset, the tester controls all circuits C1-N to capture the first response data to the reset stimulus data. Next the tester controls all circuits C1-N to shift out the first captured response data and shift in the second stimulus data. This process of capturing response data, shifting out the response data while new stimulus data is shifted in is repeated for the number of patterns (P) required to test each of the circuits 1-N. As the number of serially connected circuits (N) grows, so does the length (L) of the scan path the tester needs to traverse during each capture/shift cycle. The test time in clocks, using conventional scan testing, is equal to the sum of the scan path lengths (L) of each circuit (N) in the scan path times the number of patterns (P) to be applied.
Example 1 shows how three circuits (C1, C2, and C3) are conventionally scan tested by a tester as shown in FIG. 5. The combinational logic decode for each of the circuits C1, C2, and C3 are shown in the Tables of Example 1. The tables show the present state (PS) output (i.e. stimulus) of the scan cells (ABC) to the combinational logic and the next state (NS) input (i.e. response) to the scan cells (ABC) from the combinational logic. At the beginning of the test, the tester outputs control to reset all scan cells to a first present state (PS1). Next, the tester outputs control to all scan cells to do a first capture (CP1) of the response output of the combinational logic (CL) to the PS1 stimulus. Next, the tester outputs control to do a first 9-bit shift operation (SH1) to unload the first captured response data from each circuit""s scan cells and to load the second present state (PS2) stimulus data to each circuit""s scan cells. Next, the tester does a second capture (CP2) to load the scan cells with the response data from the second present state (PS2) stimulus data, then does a second 9-bit shift (SH2) to unload the second captured response data and load the third stimulus data. Next, the tester does a third capture (CP3) to load the scan cells with the response data from the third present state (PS3) stimulus data, then does a third 9-bit shift (SH3) to unload the third captured response data and load the fourth stimulus data (11). This process continues through an eighth capture (CP8) to load the scan cells with the response data from the eighth present state (PS8) stimulus data, then does an eighth 9-bit shift (SH8) to unload the final captured response data. The data input to the scan cells during the eighth shift (SH8) can be don""t care data (x) since testing is complete following the eighth shift. If all circuits are good the response shifted out for each PS1-8 stimulus will match the expected response as shown in the tables for C1, C2, and C3. The number of test clocks for the conventional scan testing of the circuits in example 1 is the sum of the capture clocks (CP1-8) and shift clocks (SH1-8), or 8+(8xc3x979)=80.
It is desirable to scan test electrical circuits in less time than the conventional approach.
The present invention accelerates scan testing by re-using one circuit""s scan test response data as scan test stimulus data for another circuit.